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300/sec yaw rate gyroscope with spi adis16100 rev. d information furnished by analog devices responsibility is assumed by analog device rights of third parties that may result from it license is granted by implication or otherw trademarks and registered trademarks are wood, ma 02062-9106, u.s.a. www.analog.com og devices, inc. all rights reserved. is believed to be accurate and reliable. however, no s for its use, nor for any infringements of patents or other s use. specifications subject to change without notice. no ise under any patent or patent rights of analog devices. the property of their respective owners. one technology way, p.o. box 9106, nor tel: 781.329.4700 fax: 781.461.3113 ?2006C2009 anal features complete angular rate gyroscope z-axis (yaw rate) response spi digital output interface high vibration rejection over wide frequency 2000 g -powered shock survivability externally controlled self-test internal temperature sensor output dual auxiliary 12-bit adc inputs absolute rate output for precision applications 5 v single-supply operation 8.2 mm 8.2 mm 5.2 mm package applications platform stabilization image stabilization guidance and controls inertia measurement units robotics general description the adis16100 is a gyroscope that uses the analog devices, inc., surface-micromachining process to make a functionally complete angular rate sensor with an integrated serial peripheral interface (spi). the digital data available at the spi port is proportional to the angular rate about the axis that is normal to the top surface of the package (see figure 20 ). a single external resistor can be used to increase the measurement range. an external capacitor can be used to lower the bandwidth. access to an internal temperature sensor measurement is provided through the spi for compensation techniques. two pins are available for the user to input analog signals for digitization. an additional output pin provides a precision voltage reference. two digital self-test inputs electromechanically excite the sensor to test the operation of the sensor and the signal-conditioning circuits. the adis16100 is available in an 8.2 mm 8.2 mm 5.2 mm, 16-terminal, peripheral land grid array (lga) package. functional block diagram sclk din dout cs v cc st1 filt 5v st2 com 4-channel spi 300/sec gyroscope ain2 ain1 temp sensor 1-001 mux/adc adis16100 0546 ref v ref v drive rate c out 3v to 5v figure 1.
adis16100 rev. d | page 2 of 16 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? timing specifications .................................................................. 5 ? absolute maximum ratings ............................................................ 6 ? esd caution .................................................................................. 6 ? pin configuration and function descriptions ............................. 7 ? typical performance characteristics ............................................. 8 ? theory of operation ...................................................................... 11 ? supply and common considerations ..................................... 11 ? increasing measurement range ............................................... 11 ? setting bandwidth ...................................................................... 11 ? self-test function ...................................................................... 11 ? rate sensitive axis ..................................................................... 11 ? basic operation .............................................................................. 12 ? serial peripheral interface (spi) ............................................... 12 ? applications information .............................................................. 14 ? assembly ...................................................................................... 14 ? interface board ............................................................................ 14 ? outline dimensions ....................................................................... 15 ? ordering guide .......................................................................... 15 ? revision history 6/09rev. c to rev. d changes to table 1 ............................................................................ 3 changes to table 10 and table 11 ................................................ 13 added applications information section ................................... 14 1/08rev. b to rev. c changes features .............................................................................. 1 changes to table 1 ............................................................................ 4 changes to table 3 ............................................................................ 6 changes to layout and table 4 ....................................................... 7 changes to captions figure 12 to figure 15 ................................. 9 changes to self-test function section ........................................ 11 changes to figure 22 caption ....................................................... 12 changes to table 6, table 7, table 8, and table 9 ....................... 13 6/07rev. a to rev. b changes to table 1 ............................................................................ 3 changes to table 2 ............................................................................ 5 changes to absolute maximum ratings ....................................... 6 changes to table 4 ............................................................................ 7 added figure 5 .................................................................................. 7 changes to theory of operation section .................................... 11 added basic operation section .................................................... 12 deleted second level assembly section ..................................... 14 5/06rev. 0 to rev. a changes to table 1 ............................................................................. 4 changes to setting bandwidth section ....................................... 11 changes to table 9 and table 10 .................................................. 13 1/06revision 0: initial version
adis16100 rev. d | page 3 of 16 specifications t a = 25c, v cc = v drive = 5 v, angular rate = 0/sec, c out = 0 f, 1 g , unless otherwise noted. table 1. parameter conditions in 1 typ a 1 unit sensitivity dynamic range 2 full-scale range over specifications range 300 /sec initial clockwise rotation is positive output, t a = ?40c to +85c 0.2212 0.2439 0.2717 /sec/lsb change over temperature 3 v cc = v drive = 4.75 v to 5.25 v 5 % nonlinearity best fit straight line 0.15 %fs null initial nominal 0/sec outp ut is 2048 lsb ?42 +42 /sec change over temperature 3 v cc = v drive = 4.75 v to 5.25 v 10 /sec turn-on time power-on to 0.5/sec of final value 35 ms linear acceleration effect any axis 0.2 /sec/ g voltage sensitivity v cc = v drive = 4.75 v to 5.25 v 1 /sec/v noise performance total noise 0.1 hz to 40 hz; no averaging 0.43 /sec rms rate noise density @ 25c 0.05 /sec/hz frequency response 3 db bandwidth (user-selectable) 4 c out = 0 f 40 hz sensor resonant frequency 14 khz self-test inputs st1 rateout response 5 st1 pin from logic 0 to logic 1 ?121 ?221 ?376 lsb st2 rateout response 5 st2 pin from logic 0 to logic 1 +121 +221 +376 lsb logic 1 input voltage standard high logic level definition 3.3 v logic 0 input voltage standard low logic level definition 1.7 v input impedance to common 50 k temperature sensor reading at 298 k 2048 lsb scale factor proportional to absolute temperature 0.1453 k/lsb 2.5 v reference voltage value 2.45 2.5 2.55 v load drive to ground source 100 a load regulation 0 a < i out < 100 a 5.0 mv/ma power supply rejection v cc = v drive = 4.75 v to 5.25 v 1.0 mv/v temperature drift delta from 25c 5.0 mv logic inputs input high voltage, v inh 0.7 v drive v input low voltage, v inl 0.3 v drive v input current, i in typically 10 na ?1 +1 a input capacitance, c in 10 pf analog inputs for v in < v cc resolution 12 bits integral nonlinearity ?2 +2 lsb differential nonlinearity ?2 +2 lsb offset error ?8 +8 lsb gain error ?2 +2 lsb input voltage range 0 v ref 2 v leakage current ?1 +1 a input capacitance 20 pf full power bandwidth 8 mhz
adis16100 rev. d | page 4 of 16 parameter conditions min 1 typ max 1 unit digital outputs output high voltage, v oh i source = 200 a v drive ? 0.2 v output low voltage, v ol i sink = 200 a 0.4 v conversion rate conversion time 16 sclk cycles with sclk at 20 mhz 800 ns throughput rate 1 msps power supply all at t a = ?40c to +85c v cc 4.75 5 5.25 v v drive 2.7 5.25 v v cc quiescent supply current v cc = 5 v, f sclk = 50 ksps 7.0 9.0 ma v drive quiescent supply current v drive = 5 v, f sclk = 50 ksps 70 500 a power dissipation v cc = v drive = 5 v, f sclk = 50 ksps 40 mw temperature range operation ?40 +85 c 1 all minimum and maximum specifications are guaranteed. typical specifications are neither tested nor guaranteed. 2 dynamic range is the maximum full-scale measurement range possible, including output swing range, initial offset, sensitivity, offset drift, and sensitivity drift at 5 v supplies. 3 defined as the output change from ambient to maximum temperature or ambi ent to minimum temperature. 4 frequency at which the resp onse is 3 db down from dc response. bandwidth = 1/(2 180 k (22 nf + c out )). for c out = 0 f, bandwidth = 40 hz. for c out = 1 f, bandwidth = 0.87 hz. 5 self-test response varies with temperature.
adis16100 rev. d | page 5 of 16 timing specifications t a = 25c, angular rate = 0/sec, unless otherwise noted. 1 table 2. parameter v cc = v drive = 5 v unit description f sclk 2 10 khz min 20 mhz max t convert 16 t sclk t quiet 50 ns min minimum quiet time required between cs rising edge and start of next conversion. t 2 10 ns min cs to sclk setup time. t 3 3 30 ns max delay from cs until dout three-state disabled. t 4 3 40 ns max data access time after sclk falling edge. t 5 0.4 t sclk ns min sclk low pulse width. t 6 0.4 t sclk ns min sclk high pulse width. t 7 10 ns min sclk to dout valid hold time. t 8 4 15/35 ns min/max sclk falling ed ge to dout high impedance. t 9 10 ns min din setup time prior to sclk falling edge. t 10 5 ns min din hold time after sclk falling edge. t 11 20 ns min 16 th sclk falling edge to cs high. 1 guaranteed by design. all input signals are specified with t r and t f = 5 ns (10% to 90% of v cc ) and timed from a voltage level of 1.6 v. the 5 v operating range spans from 4.75 v to 5.25 v. 2 mark/space ratio for the sc lk input is 40/60 to 60/40. 3 measured with the load circuit in figure 3 and defined as the time required for the output to cross 0.4 v or 0.7 v drive . 4 t 8 is derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit in figure 3. the meas ured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. the time, t 8 , quoted in the timing specifications is the true bus relinquis h time of the part and is independent of the bus loading. 1 2 3 4 5 6 11 12 13 14 15 16 b sclk dout din cs zero add1 add0 d db2 db1 db0 low write dontc dontc c dontc dontc dontc b11 db10 db4 db3 add1 add0 coding dont address bits zero three-state three-state t 2 t 3 t 4 t 9 t 6 t convert t 5 t 8 t 11 t quiet t 7 t 10 05461-002 05461-003 figure 2. gyroscope serial interface timing diagram 200a i ol 200a i oh 1.6v to output pin c l 50pf figure 3. load circuit for digita l output timing specifications
adis16100 rev. d | page 6 of 16 absolute maximum ratings table 3. parameter rating acceleration (any axis, unpowered, 0.5 ms) 2000 g acceleration (any axis, powered, 0.5 ms) 2000 g v cc to com ?0.3 v to +6.0 v v drive to com ?0.3 v to v cc + 0.3 v analog input voltage to com ?0.3 v to v cc + 0.3 v digital input voltage to com ?0.3 v to +7.0 v digital output voltage to com ?0.3 v to v cc + 0.3 v st1/st2 input voltage to com ?0.3 v to v cc + 0.3 v operating temperature range ?40c to +85c storage temperature range ?65c to +150c stresses above those listed under the absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. drops onto hard surfaces can cause shocks of greater than 2000 g and exceed the absolute maximum rating of the device. care should be exercised in handling to avoid damage. esd caution
adis16100 rev. d | page 7 of 16 05461 pin configuration and fu nction descriptions -020 filt rate v drive ain1 nc dout sclk din ain2 com v ref st2 adis16100 top look through view (not to scale) 16 nc v cc st1 cs 15 14 13 5 6 7 8 4 3 2 1 9 10 11 12 pin 1 indicator notes 1. nc = no connect 2 . this is not an actual top view, as the pins are not visible f r om the top. this is a layout view, which represents the pin configuration, if the package is looked through from the top. this configuration is provided for pcb layout purposes. 461-018 0.6700 bsc 12 3.6865 bsc 8 2.5050 bsc 8 0.5000 bsc figure 4. pin configuration, top look through view 05 16 5.010 bsc 4 7.373 bsc 2 1.000 bsc 16 figure 5. second-level assembly pad layout table 4. pin function descriptions pin no. nemonic type 1 description 1 din i spi data input. 2 sclk i spi serial clock. 3 dout o spi data output. 4 nc no connect. 5 rate o buffered analog output. re presents the angular rate signal. 6 filt i external capacitor connection to control bandwidth. 7 v drive s digital interface supply. to simplify interfacing, this can be the receive processing supply of the circuit. 8 ain1 i external analog input channel 1. see add0 and add1 address bits in table 5 . 9 ain2 i external analog input channel 2. see add0 and add1 address bits in table 5 . 10 com s common. reference point for all circuitry in the adis16100. 11 v ref o precision 2.5 v reference. 12 st2 i self-test input 2. 13 st1 i self-test input 1. 14 v cc s analog power. 15 nc no connect. 16 cs i chip select. active low. this input frames the serial data transfer and initiates the conversion process. 1 i = input; o = output; s = power supply.
adis16100 rev. d | page 8 of 16 1845 null (lsb) typical performance characteristics 30 0 05461-004 percent of population (%) 25 20 15 10 5 60 0 6.2 05461-007 supply current (ma) percent of population (%) 50 40 30 20 10 1895 1945 1995 2045 2095 2145 2195 2245 figure 6. initial null histogram 2250 1850 05461-005 null level (lsb) 6.3 6.4 6.5 6.6 6.7 6.8 6.9 7.0 figure 9. supply current histogram 80 0 05461-008 st1 (lsb) percent of population (%) 4.7 5.3 v cc (v) 2200 2150 2100 2050 2000 1950 1900 70 60 50 40 30 20 10 4.8 4.9 5.0 5.1 5.2 +85c ?40c +25c figure 7. null level vs. supply voltage 2040 1970 05461-006 null level (lsb) ?371 ?346 ?321 ?296 ?271 ?246 ?221 ?196 ?171 ?146 ?121 figure 10. self-test 1 histogram 80 0 05461-009 st2 (lsb) percent of population (%) ?50 100 temperature (c) 2030 2020 2010 2000 1990 1980 ?20104070 30 part average, v cc = 4.75v 30 part average, v cc = 5v 30 part average, v cc = 5.25v figure 8. null level vs. temperature 70 60 50 40 30 20 10 121 146 171 196 221 246 271 296 321 346 371 figure 11. self-test 2 histogram
adis16100 rev. d | page 9 of 16 0 4.7 5.3 05461-010 self-test level (lsb) 400 v cc (v) ? 150 ?250 ?50 10 0 05461-013 temperature (c) self-test level (lsb) 350 300 250 200 150 100 50 4.8 4.9 5.0 5.1 5.2 +85c +25c ?40c figure 12. self-test 2 level vs. supply voltage 0 self-test level (lsb) ?400 4.7 5.3 05461-011 v cc (v) ?50 ?100 ?150 ?200 ?250 ?300 ?350 4.8 4.9 5.0 5.1 5.2 +85c ?40c +25c figure 13. self-test 1 level vs. supply voltage 250 2 self-test level (lsb) 150 ?50 100 05461-01 temperature (c) 240 230 220 210 200 190 180 170 160 ?20 10 40 70 30 part average, v cc = 4.75v 30 part average, v cc = 5v 30 part average, v cc = 5.25v figure 14. self-test 2 vs. temperature ?160 ?170 ?180 ?190 ?200 ?210 ?220 ?230 ?240 ?20104070 30 part average, v cc = 4.75v 30 part average, v cc = 5v 30 part average, v cc = 5.25v 3 ?3 ?50 100 05461-014 temperature (c) offset level (lsb) figure 15. self-test 1 vs. temperature ?20 10 40 70 2 1 0 ?1 ?2 30 part average, v cc = 4.75v 30 part average, v cc = 5v 30 part average, v cc = 5.25v 3 ?3 05461-015 gain error (lsb) figure 16. adc offset level vs. temperature and supply voltage ?50 100 temperature (c) ?20104070 30 part average, v cc = 4.75v 30 part average, v cc = 5v 30 part average, v cc = 5.25v 2 1 0 ?1 ?2 figure 17. adc gain error vs. temperature (excluding v ref )
adis16100 rev. d | page 10 of 16 2.490 4.7 5.3 05461-0 v cc (v) 2.500 16 v ref level (v) 2.499 2.498 2.497 2.496 2.495 2.494 2.493 2.492 2.491 4.8 4.9 5.0 5.1 5.2 +85c +25c ?40c figure 18. v ref level vs. supply voltage 2060 2055 0 05461-017 2050 2045 2040 1000 2000 3000 4000 5000 6000 7000 8000 000001111111011x 000001111111100x 000001111111101x 000001111111110x 000001111111111x 000010000000000x 000010000000001x 000010000000010x 000010000000011x 000010000000100x 000010000000101x 000010000000110x 1 0 5 9 339 1307 4132 1996 387 12 3 1 samples = 8192, spread = 23, std dev = 1.695, mean = 2050.682 figure 19. noise histogram
adis16100 rev. d | page 11 of 16 theory of operation the adis16100 operates on the principle of a resonator gyroscope. two polysilicon sensing structures each contain a dither frame that is electrostatically driven to resonance. this produces the necessary velocity element to produce a coriolis force while rotating. at two of the outer extremes of each frame, orthogonal to the dither motion, are movable fingers that are placed between fixed pickoff fingers to form a capacitive pickoff structure that senses coriolis motion. the resulting signal is fed to a series of gain and demodulation stages that produce the electrical rate signal output. the rate signal is then converted to a digital representation of the output on the spi pins. the dual- sensor design rejects external g forces and vibration. fabricating the sensor with the signal conditioning electronics preserves signal integrity in noisy environments. the electrostatic resonator requires 14 v to 16 v for operation. because only 5 v is typically available in most applications, a charge pump is included on-chip. after the demodulation stage, there is a single-pole, low-pass filter included on-chip that is used to limit high frequency artifacts before final amplification. the frequency response is dominated by the second low-pass filter, which is set at 40 hz. for additional bandwidth reduction options, see the setting bandwidth section. supply and common considerations power supply noise and transient behaviors can influence the accuracy and stability of any sensor-based measurement system. when considering the power supply for the adis16100, it is important to understand that the adis16100 provides 0.2 f of decoupling capacitance on the v cc pin. depending on the level of noise present in the system power supply, the adis16100 may not require any additional decoupling capacitance for this supply. the analog supply, v cc , and the digital interface supply, v drive , are segmented to allow multiple logic levels to be used in receiving the digital output data. v drive is intended for the downstream logic power supply and supports standard 3.3 v and 5 v logic families. the v drive supply does not have internal decoupling capacitors. increasing measurement range the full-scale measurement range of the adis16100 is increased by placing an external resistor between the rate pin and filt pin, which results in a parallel connection with the internal 180 k, 1% resistor. for example, a 330 k external resistor gives ~50% increase in the full-sca le range. this is effective for up to a 4 increase in the full-scale range (minimum value of the parallel resistor allowed is 45 k). the internal circuitry headroom requirements prevent further increase in the linear full-scale output range. the trade-offs associated with increasing the full-scale range are potential increase in output null drift (as much as 2/sec over temperature) and introducing initial null bias errors that must be calibrated. setting bandwidth an external capacitor can be used in combination with an on-chip resistor to create a low-pass filter to limit the bandwidth of the adis16100 rate response. the ?3 db frequency is defined as ( ( ) ) = f0.022 21/ + out out out cr f where: r out is the internal impedance that was trimmed during manufacturing to 180 k 1%. c out is the external capacitance across the rate and filt pins. any external resistor applied between rate and filt results in ( ) ( ) ext ext out r r r + = k 180/ k 180 05461-019 where r ext is the external resistor. with c out = 0 f, a default ?3 db frequency response of 40 hz is obtained based upon an internal 0.022 f capacitor implemented on-chip. self-test function the adis16100 includes a self-test feature that actuates each of the sensing structures and associated electronics in the same manner as if subjected to an angular rate. it provides a simple method for exercising the mechanical structure of the sensor, along with the entire signal processing circuit. it is activated by standard logic high levels applied to input st1, input st2, or both. st1 causes a change in the digital output equivalent to typically ?221 lsb, and st2 causes an opposite +221 lsb change. the self-test response follows the viscosity temperature dependence of the package atmosphere, approximately 0.25%/c. activating both st1 and st2 simultaneously is not damaging. because st1 and st2 are not necessarily closely matched, actuating both simultaneously can result in an apparent null bias shift. continuous self-test as an additional failure detection measure, a power-on self-test can be performed. however, some applications warrant a continuous self-test while sensing rate. rate sensitive axis rateout +2047 lsb ?2048 lsb 1 4 5 8 longitudinal axis rate axis clock-wise rotation lateral axis figure 20. rate signal increa ses with clockwise rotation
adis16100 rev. d | page 12 of 16 basic operation the adis16100 is designed for simple integration into indus- trial system designs, requiring only a 5.0 v power supply and a 4-wire, industry standard serial peripheral interface (spi). the spi handles all digital input/output communications in the adis16100. serial peripheral interface (spi) the adis16100 spi port includes four signals: chip select ( cs ), serial clock (sclk), data input (din), and data output (dout). the cs line enables the adis16100 spi port and frames each spi event. when this signal is high, the dout lines are in a high impedance state and the signals on din and sclk have no impact on operation. a complete data frame contains 16 clock cycles. because the spi port operates in full duplex mode, it supports simultaneous, 16-bit receive (din) and transmit (dout) functions within the same data frame. control register the din control register provides controls for two operational settings: the output data source and the coding (twos comple- ment vs. offset binary). table 5 and figure 22 provide the proper bit definitions for the control register configuration. the din sequence starts with a 1 for configuration sequences and a 0 for read sequences. when this bit is 0, the remaining din bits do not change the control register and the next samples output data reflects the existing configuration. data loads from the din pin into the adis16100 on the falling edge of sclk. when the 16 sclk sequence is complete, the control register is updated and ready for the next read sequence. if a data frame has less than 16 sclk cycles, the control register does not update and maintains its previous configuration. the din bit definitions in table 5 , which have either 0 or 1 assigned to them, are critical for proper operation. adc conversion the chip select ( cs ) and serial clock (sclk) lines control the on-board analog-to-digital conversion process. when the chip select line goes low, the dout line comes out of three-state mode, the track-and-hold goes into hold mode, and the adc samples the analog input at this point. the track-and-hold returns to track mode on the 14 th falling edge of the sclk line. the serial clock drives the internal adc conversion clock, using its falling edge for control of this process. all 16 sclk cycles are required for a complete conversion. if a data frame has less than 16 sclk cycles, the conversion cannot complete and does not update the output data for the next data frame cycle. output data access the dout sequence starts with two zeros, one that clocks out after the falling edge of cs , and another that clocks out on the first sclk falling edge. the next 14 bits, add0, add1, and the 12 data bits, clock out on sclk falling edges. after the 16 th falling edge, the dout line moves to a three-state mode. when setting up the system process to receive data from the adis16100, use a clock phase setting of 0 and a clock polarity setting of 0. these settings reflect the timing displayed in figure 22 . to maintain proper communication at the maximum specified clock rates, the system processor must be able to support the setup time requirement listed in figure 2 and table 2 (t 9 ). cs sclk din dout configuration command for next output sequence data frame data frame next command, if necessary data output, based on previous configuration 05461-021 figure 21. configuration and read sequence d/c d/c d/c d/c d/c d/c d/c add1 add0 d/c 1 1 0 0 cs sclk din adc placed in hold mode adc placed in track mode write code 1 2 3 4 5 6 7 8 9 1011 1213 141516 05461-022 d11 add0 add1 0 0 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dout figure 22. spi sequence, clock polarity = 0, clock phase = 0
adis16100 rev. d | page 13 of 16 table 5. din bit assignments bit no. mnemonic comment 15 write 1: write contents on din to control register. 0: no changes to control register. 14 0 low state for normal operation. 13, 12 d/c dont care. 11, 10 add1, add0 data source setting. 00: gyroscope output. 01: temperature output. 10: analog input 1. 11: analog input 2. 9, 8 1 high state for normal operation. 7, 6 d/c dont care. 5 0 low state for normal operation. 4 code output data format setting. 0: twos complement. 1: offset binary. 3 to 0 d/c dont care. output coding examples table 6. gyroscope data coding, twos complement angular rate (/sec) code bit pattern 300 1230 0000010011001110 0.4878 2 0000000000000010 0.2439 1 0000000000000001 0 0 0000000000000000 ?0.2439 ?1 0000111111111111 ?0.4878 ?2 0000111111111110 ?300 ?1230 0000101100110010 table 7. gyroscope data coding, offset binary angular rate (/sec) code bit pattern 300 3278 0000110011001110 0.4878 2050 0000100000000010 0.2439 2049 0000100000000001 0 2048 0000100000000000 ?0.2439 2047 0000011111111111 ?0.4878 2046 0000011111111110 ?300 818 0000001100110010 table 8. temperature data coding, twos complement temperature (c) code bit pattern 85 413 0001000110011101 25 + 0.2906 2 0001000000000010 25 + 0.1453 1 0001000000000001 25 0 0001000000000000 25 ? 0.1453 ?1 0001111111111111 25 ? 0.2906 ?2 0001111111111110 ?40 ?447 0001111001000001 table 9. temperature data coding, offset binary temperature (c) code bit pattern 85 2461 0001100110011101 25 + 0.2906 2050 0001100000000010 25 + 0.1453 2049 0001100000000001 25 2048 0001100000000000 25 ? 0.1453 2047 0001011111111111 25 ? 0.2906 2046 0001011111111110 ?40 1601 0001011001000001 table 10. adc data coding, twos complement input level (v) code 1 bit pattern 4.5 1638 0010011001100110 2.5 + 0.002442 2 0010000000000010 2.5 + 0.001221 1 0010000000000001 2.5 0 0010000000000000 2.5 ? 0.001221 ?1 0010111111111111 2.5 ? 0.002442 ?2 0010111111111110 0.5 ?1638 0010100110011010 1 code for bits [4:3] assume ain1 (bits [4:3] = 11 for ain2). table 11. adc data coding, offset binary input level (v) code 1 bit pattern 4.5 3686 0010011001100110 2.5 + 0.002442 2050 0010100000000010 2.5 + 0.001221 2049 0010100000000001 2.5 2048 0010100000000000 2.5 ? 0.001221 2047 0010011111111111 2.5 ? 0.002442 2046 0010011111111110 0.5 410 0010000110011010 1 code for bits [4:3] assume ain1 (bits [4:3] = 11 for ain2).
adis16100 rev. d | page 14 of 16 applications information assembly the adis16100 is a system-in-pa ckage (sip) that integrates multiple components in a land grid array (lga). this config- uration offers the convenience of solder-reflow installation on printed circuit boards (pcbs). when developing a process flow for installing adis16100 devices on pcbs, see jedec standard document, j-std-020c, for refl ow temperature profile and processing information. the adis16100 can use the sn-pb eutectic process from this standard. see jedec j-std-033 for moisture sensitivity (msl) handling requirements. the msl rating for these devices is marked on the antistatic bags, which protect these devices from esd during shipping and handling. prior to assembly, review the process flow for information about introducing shock levels that exceed the adis16100s absolute maximum ratings. some pcb separation and ultrasonic cleaning processe s are common areas that can introduce high levels of shock to these devices. interface board the adis16100/pcbz (see the ordering guide) provides the adis16100 functionality on a 1.2 inch 1.3 inch printed circuit board, which simplifies the connection to an existing processor system. the four mounting holes accommodate either m2 (2 mm) or 2-56 machine screws. these boards are made of is410 material and are 0.063 inches thick. the second level assembly uses a snpb63/37-compatible solder composition, which has a presolder reflow thickness of approximately 0.005 inches. the pad pattern on the adis16100/pcbz matches figure 5. j1 and j2 are dual- row, 2 mm (pitch) connectors that work with several ribbon cable systems, including 3m part number 152212-0100-gb (ribbon-crimp connector) and 3m part number 3625/12 (ribbon cable). 2 sclk 3 dout 13 din 16 1 12 st2 11 v ref 8 ain1 9 ain2 6 filt 5 rate 4 15 10 adis16100 7 v drive nc nc gnd 11 12 9 10 7 8 5 6 3 4 1 2 cs st1 c1 1f 14 v cc c4 1f c2 1f c3 1f 11 12 9 10 7 8 5 6 3 4 1 2 j1 j2 05461-118 figure 23. electrical schematic i sensor u1 j1 c1 j2 1.050 2 0.925 2 0.673 2 0.000 0.150 0.200 0.035 2 0.000 0.865 2 0.900 1.100 4 ?0.087 m20.4 a 0 5461-117 figure 24. pcb assembly view and dimensions
adis16100 rev. d | page 15 of 16 022107- outline dimensions b side view top view bottom view pin 1 indicator 0.873 bsc (16 ) 5.20 max 8.20 typ 1 4 5 8 9 12 13 16 8.35 max 5.010 bsc (4 ) 2.505 bsc (8 ) 7.00 typ 7.373 bsc (2 ) 0.200 min (all sides ) 0.797 bsc (12 ) 0.373 bsc (16 ) figure 25. 16-terminal stacked land grid array [lga] (cc-16-1) dimensions shown in millimeters ordering guide model temperature range packag e description package option adis16100acc ?40c to +85c 16-terminal stacked land grid array (lga) cc-16-1 adis16100/pcb evaluation board
adis16100 rev. d | page 16 of 16 notes ?2006C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05461-0-6/09(d)

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